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d a t a sh eet preliminary speci?cation supersedes data of june 1994 file under integrated circuits, ic02 1996 nov 04 integrated circuits saa5281 integrated video input processor and teletext decoder (ivt1.8*)
1996 nov 04 2 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 features complete teletext and vps decoding in a single package built-in 8k 8 memory for up to 8 page storage enhanced mode allows 7 fastext pages and 8 pages of top to be captured ability to request only subtitle pages acquisition and decoding of vps data data valid output available to indicate reception of error-free vps or packet 8/30/2 data software and hardware compatible with saa5246 and saa5248 meshing display within boxes separate data checking algorithms and pointers for each acquisition channel 24 : 18 hamming checker automatic packet 26 extension character processing indication of line 23 for external use 13.5 mhz clock output to drive external microcontroller detection of spanish transmissions to disable flicker-stopper compatible with philips one-chip tv ic (tda836x) for scan-locking applications. description the ivt1.8* is a single-chip teletext decoder ic for decoding 625-line based world system teletext transmissions. the device is based on ivt1.0vps and has reception facilities for the 5 mhz biphase vps signal. it is intended for use in video recorders, in particular to implement the vpt facility (vcr programming via teletext). with suitable software both vpt standards (ebu pdc system a and system b) can be accommodated to allow operation from any european vpt transmission. automatic processing of packet 26 transmissions is also possible. no external memory is required as an 8k 8 dram is included on-chip for up to 8 page storage. an enhanced mode allows 7 fastext pages to be stored, with one chapter used to store extension packets. quick reference data ordering information symbol parameter min. typ. max. unit v dd supply voltage 4.5 5.0 5.5 v i dd supply current - 75 150 ma v sync sync voltage amplitude 0.1 0.3 0.6 v v vid(p-p) video input voltage amplitude (peak-to-peak value) 0.7 1.0 1.4 v f xtal crystal frequency - 27 - mhz t amb operating ambient temperature - 20 - +70 c type number package name description version saa5281p dip48 plastic shrink dual in-line package; 32 leads (400 mil) sot240-1 SAA5281ZP sdip52 plastic shrink dual in-line package; 52 leads (600 mil) sot247-1 saa5281gp qfp64 plastic quad ?at package; 64 leads (lead length 1.95 mm); body 14 20 2.8 mm sot319-2
1996 nov 04 3 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 block diagram fig.1 block diagram; pin numbers for dip48 (sot240-1). handbook, full pagewidth mbd783 analog reference generator analog to digital converter input clamp and sync separator analog output buffer 27 mhz clock generator 7 8 12 36 2 3 37 11 4 display clock phase-locked loop 13 teletext or vps control data slicer and clock regenerator 14 25 5 timing chain 44 serial-to -parallel converter teletext aquisition and decoding vps acquisition and decoding interface i c-bus 2 23 24 24 to 18 hamming decoder packet 26 processing engine 21 power-on reset dram refresh and timing 8k x 8 dram display 22 19 20 18 15 16 17 110 v dd1 v dd2 y blan cor rgbref rgb odd/even (or dv) ref iref 6 9 v ss1 cvbs black sttv/lfb v ss2 v ss3 clk en oscout oscin oscgnd clk o/p pol vcr/ffb line 23 sda scl saa5281 memory interface
1996 nov 04 4 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 pinning symbol pin description sot240-1 sot247-1 sot319-2 v dd1 1 52 11 +5 v supply 1 oscout 2 1 13 27 mhz crystal oscillator output oscin 3 2 14 27 mhz crystal oscillator input oscgnd 4 3 15 0 v crystal oscillator ground v ss1 5 4 and 5 16 0 v ground ref+ 6 6 18 positive reference voltage for adc; this pin should be connected to ground via a 100 nf capacitor black 7 8 19 video black level storage input/output; this pin should be connected to ground via a 100 nf capacitor cvbs 8 9 20 composite video input; a positive-going 1 v (peak-to-peak) input is required, connected via a 100 nf capacitor iref 9 10 21 reference current input, connected to ground via a 27 k w resistor v dd2 10 11 22 +5 v supply 2 pol 11 12 23 sttv/lfb/ffb polarity selection input sttv/lfb 12 13 24 sync to tv output line ?yback input; function controlled by an internal register bit (scan sync mode) vcr/ffb 13 14 27 pll time constant switch/?eld input; function controlled by an internal register bit (scan sync mode) v ss2 14 15 28 0 v ground; connected to v ss1 for normal operation r 15 16 30 dot rate character output of the red colour information g 16 17 32 dot rate character output of the green colour information b 17 18 33 dot rate character output of the blue colour information rgbref 18 19 34 input dc voltage to de?ne the output high level on the rgb pins blan 19 20 35 dot rate fast blanking output cor 20 21 36 programmable output to provide contrast reduction of the tv picture for mixed text and picture displays or when viewing news?ash/subtitle pages; open-drain output odd/even (or dv) 21 22 37 in odd/even mode a 25 hz output synchronized with the cvbs input ?eld sync pulses to produce a non-interlaced display by adjustment of the vertical de?ection currents; in dv mode a vpt data valid signal is used to indicate reception of error-free vps or 8/30 format 2 data y 22 23 38 dot rate character output of teletext foreground colour information; open-drain output scl 23 24 39 serial clock input for i 2 c-bus; it can still be driven high during power-down of the device sda 24 25 40 serial data port for the i 2 c-bus, open-drain output; it can still be driven high during power-down of the device v ss3 25 26 44 0 v ground
1996 nov 04 5 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 i.c. 26 to 35, 38 to 43, 45 to 48 27 to 32, 35 to 38, 41 to 46, 48 to 51 1to3, 5to8, 45 to 53, 55, 61, 63 to 64 internally connected; normally open-circuit clk en 36 39 56 clock enable input to enable the clock output (clp o/p pin 37); internal pull-down normally disables clock clk o/p 37 40 59 13.5 mhz clock output to drive an external microcontroller line 23 44 47 4 output for indication of line 23 for use with external circuitry n.c. - 7, 33, 34 9, 10, 12, 17, 25, 26, 29, 31, 41 to 43, 54, 57, 58, 60, 62 not connected; normally open-circuit symbol pin description sot240-1 sot247-1 sot319-2
1996 nov 04 6 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 fig.3 pin configuration; sot247-1 (sdip52). handbook, halfpage 1 2 3 4 5 6 7 8 9 10 11 12 13 40 39 38 37 36 35 34 33 32 31 30 29 28 27 14 15 16 17 18 19 20 22 23 24 25 26 21 42 41 43 44 45 46 47 48 49 50 51 52 i.c. i.c. i.c. i.c. i.c. i.c. i.c. i.c. i.c. clk o/p line 23 clk en i.c. i.c. n.c. n.c. i.c. i.c. i.c. i.c. i.c. i.c. v ss3 oscout oscin oscgnd ref+ n.c. black cvbs iref v dd2 pol v ss1 v ss1 sttv/lfb vcr/ffb v ss2 r g b rgbref blan cor odd/even (or dv) y scl sda i.c. i.c. i.c. v dd1 mbd785 saa5281 fig.2 pin configuration; sot240-1 (dip48). handbook, halfpage 1 2 3 4 5 6 7 8 9 10 11 12 13 40 39 38 37 36 35 34 33 32 31 30 29 28 27 14 15 16 17 18 19 20 22 23 24 26 25 21 42 41 43 44 45 46 47 48 i.c. i.c. i.c. i.c. i.c. i.c. i.c. i.c. i.c. i.c. clk o/p line 23 clk en i.c. i.c. i.c. i.c. i.c. i.c. i.c. i.c. i.c. i.c. v ss3 saa5281 oscout oscin oscgnd ref+ black cvbs iref v dd2 pol v ss1 sttv/lfb vcr/ffb v ss2 r g b rgbref blan cor y scl sda odd/even (or dv) v dd1 mbd784
1996 nov 04 7 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 fig.4 pin configuration; sot319-2 (qfp64). handbook, full pagewidth saa5281 mbh665 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 v dd1 v ss1 oscout i.c. i.c. i.c. line 23 i.c. i.c. i.c. i.c. n.c. n.c. n.c. n.c. oscin oscgnd black b rgbref blan cor y scl sda n.c. n.c. n.c. i.c. i.c. i.c. i.c. i.c. i.c. i.c. i.c. i.c. i.c. clk en clk o/p i.c. n.c. n.c. n.c. n.c. n.c. i.c. i.c. v ss3 cvbs iref pol n.c. n.c. n.c. n.c. sttv/lfb r g vcr/ffb v dd2 v ss2 ref + odd/even (or dv)
1996 nov 04 8 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 quality and reliability this device will meet philips semiconductors general quality specification for business group consumer integrated circuits snw-fq-611-part e . the principal requirements are shown in tables 1 to 4. group a table 1 acceptance tests per lot group b table 2 processability tests (by package family) group c table 3 reliability tests (by process family) table 4 reliability tests (by device type) notes to tables 1 to 4 1. ppm = fraction of defective devices, in parts per million. ltpd = lot tolerance percent defective. fpm = fraction of devices failing at test condition, in failures per million. fits = failures in time standard. test requirements (1) mechanical cumulative target: < 100 ppm electrical cumulative target: < 100 ppm test requirements (1) solderability < 7% ltpd mechanical < 15% ltpd solder heat resistance < 15% ltpd test conditions requirements (1) operational life 168 hours at t j = 150 c < 1500 fpm; equivalent to < 100 fits at t j =70 c humidity life temperature, humidity, bias 1000 hours, 85 c, 85% rh (or equivalent test) < 2000 fpm temperature cycling performance t stg(min) to t stg(max) < 2000 fpm test conditions requirements (1) esd and latch-up esd human body model 2000 v, 100 pf, 1.5 k w < 15% ltpd esd machine model 200 v, 200 pf, 0 w < 15% ltpd latch-up 100 ma, 1.5 v dd (absolute maximum) < 15% ltpd
1996 nov 04 9 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 limiting values in accordance with absolute maximum rating system (iec 134). characteristics v dd = 5 v 10%; t amb = - 20 to +70 c; pin numbers refer dip48 package; unless otherwise speci?ed. symbol parameter min. max. unit v dd supply voltage (all supplies) - 0.3 +6.5 v v i input voltage (any input) - 0.3 v dd + 0.5 v v o output voltage (any output) - 0.3 v dd + 0.5 v i o output current (each output) - 10 ma i iok dc input or output diode current - 20 ma t amb operating ambient temperature - 20 +70 c symbol parameter conditions min. typ. max. unit supplies v dd supply voltage 4.5 5.0 5.5 v i ddtot total supply current - 75 150 ma inputs cvbs v sync sync voltage amplitude 0.1 0.3 0.6 v v burst(p-p) colour burst amplitude (peak-to-peak value) 0.0 0.3 4.0 v t d(sync) delay from cvbs to tcs output from sttv buffer (nominal video, average of leading/trailing edge) - 150 0 +150 ns d t d(sync) change in sync delay between all black and all white video input at nominal levels 0 - 25 ns v vid(p-p) video input voltage amplitude (peak-to-peak value) 0.7 1.0 1.4 v v dat(text) teletext data voltage amplitude 0.29 0.46 0.71 v d f/f display pll capture range 7 -- % z source source impedance -- 250 w v i input switching voltage level of sync separator 1.7 2.0 2.3 v z i input impedance 2.5 5.0 - k w c i input capacitance -- 10 pf iref r gnd resistor to ground - 27 - k w v i input voltage - 0.5v dd - v
1996 nov 04 10 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 pol v il low level input voltage - 0.3 - +0.8 v v ih high level input voltage 2.0 - v dd + 0.5 v i li input leakage current v i = 0 to v dd - 10 - +10 m a c i input capacitance -- 10 pf lfb v il low level input voltage - 0.3 - tbf v v ih high level input voltage tbf - v dd + 0.5 v i li input leakage current v i = 0 to v dd - 10 - +10 m a i imax maximum input current note 1 - 1 - +1 ma t dlfb delay between lfb front edge and input video line sync - 250 - ns vcr/ffb v il low level input voltage - 0.3 - +0.8 v v ih high level input voltage 2.0 - v dd + 0.5 v i li input leakage current v i = 0 to v dd - 10 - +10 m a i imax maximum input current note 1 - 1 - +1 ma rgbref v il low level input voltage - 0.3 - v dd v i li input leakage current v i = 0 to v dd - 10 - +10 m a scl v il low level input voltage - 0.3 - +1.5 v v ih high level input voltage 3.0 - v dd + 0.5 v i li input leakage current v i = 0 to v dd - 10 - +10 m a c i input capacitance -- 10 pf f clk clock frequency 0 - 100 khz t r input rise time between 10% and 90% -- 2 m s t f input fall time between 90% and 10% -- 2 m s inputs/outputs c rystal oscillator (oscin; oscout) v osc(p-p) oscillator voltage amplitude (peak-to-peak value) - 1.0 - v g v small signal voltage gain - 1.0 - g m mutual conductance 5.0 -- ms c i input capacitance -- 10 pf c fb feedback capacitance - 1 - pf symbol parameter conditions min. typ. max. unit
1996 nov 04 11 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 black c black storage capacitor to ground - 100 - nf v black black level voltage for nominal sync amplitude 1.8 2.15 2.5 v i li input leakage current v i = 0 to v dd - 10 - +10 m a sda ( open - drain input / output ) v il low level input voltage - 0.3 - +1.5 v v ih high level input voltage 3.0 - v dd + 0.5 v v ol low level output voltage i ol = 3 ma 0 - 0.5 v i li input leakage current v i = 0 to v dd - 10 - +10 m a c i input capacitance -- 10 pf c l load capacitance -- 400 pf t r input rise time between 10% and 90% -- 2 m s t f input fall time between 90% and 10% -- 2 m s t f output fall time between 3 v and 1 v -- 200 ns outputs sttv g sttv gain of sttv relative to video input 0.9 1.0 1.1 v tcs tcs voltage amplitude 0.2 0.3 0.45 v d v tcs dc shift between tcs output and nominal video output -- 0.15 v i o output drive current -- 3.0 ma c l load capacitance -- 100 pf r, g and b v ol low level output voltage i ol = 2 ma 0 - 0.2 v v oh high level output voltage i oh = - 1.6 ma; v rgbref < v dd - 2v; note 2 v rgbref - 0.25 v rgbref v rgbref + 0.5 v | z o | output impedance -- 200 w c l load capacitance -- 50 pf t r output rise time between 10% and 90% -- 20 ns t f output fall time between 90% and 10% -- 20 ns blan v ol low level output voltage i ol = 1.6 ma 0 - 0.4 v v oh high level output voltage i oh = - 0.2 ma 1.1 -- v i oh =0ma -- 2.8 v c l load capacitance -- 50 pf t r output rise time between 10% and 90% -- 20 ns t f output fall time between 90% and 10% -- 20 ns symbol parameter conditions min. typ. max. unit
1996 nov 04 12 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 notes 1. this current is the maximum allowed into the inputs when line and field flyback signals are connected to these inputs. series current limiting resistors must be used to limit the input currents to 1 ma. 2. voltage level v oh for r, g and b outputs is taken to be the mean value during the output high time. if higher r, g and b voltage v oh levels are required rgbref voltage level may be raised and a pull-up resistor used at each of these pins provided current specification (i ol ) is not exceeded. odd/even or dv v ol low level output voltage i ol = 1.6 ma 0 - 0.4 v v oh high level output voltage i oh = - 1.6 ma v dd - 0.4 - v dd v c l load capacitance -- 120 pf t r output rise time between 0.6 v and 2.2 v -- 50 ns t f output fall time between 0.6 v and 2.2 v -- 50 ns cor and y( open - drain outputs ) v oh high level pull-up output voltage -- v dd v v ol low level output voltage i ol = 2 ma 0 - 0.4 v i ol = 5 ma 0 - 1.0 v c l load capacitance -- 25 pf t f output fall time load resistor of 1.2 k w to v dd ; measured between v dd - 0.5 v and 1.5 v -- 50 ns i lo output leakage current v i = 0 to v dd - 10 - +10 m a t skew skew delay between display outputs r, g, b, cor, y and blan -- 20 ns i 2 c-bus timing (see fig.5) t low scl clock low time 4.0 --m s t high scl clock high time 4.0 --m s t su;dat data set-up time 250 -- ns t hd;dat data hold time 170 -- ns t su;sto set-up time from clock high to stop 4.0 --m s t buf start set-up time following a stop 4.0 --m s t hd;sta start hold time 4.0 --m s t su;sta start set-up time following a clock low-to-high transition 4.0 --m s symbol parameter conditions min. typ. max. unit
1996 nov 04 13 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 fig.5 i 2 c-bus timing. handbook, full pagewidth mbc764 t buf t f t high t su;dat t su;sto t hd;dat t su;sta t r t low t hd;sta sda scl sda timing chain fig.6 display output timing (a) line rate (b) field rate. (1) also blan in character and box blanking. handbook, full pagewidth 0 4.66 0 0 lsp mla662 - 1 (tcs) 16.67 41 r, g, b, y (1) r, g, b, y (1) display period display period lines 42 to 291 inclusive (and 355 to 604 inclusive interlaced) 291 312 line numbers 56.67 m s 40 m s 64 m s
1996 nov 04 14 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 handbook, full pagewidth 0 4.66 0 2.33 0 32 34.33 27.33 32 64 m s 59.33 621 (308) 622 (309) 623 (310) 624 (311) 625 (312) 1 2 3456 7 308 309 310 311 312 1 2 3 4 5 6 7 309 310 311 312 313 314 (1) 315 (2) 316 (3) 317 (4) 318 (5) 319 (6) 320 (7) lsp (line sync pulse) ep (equalizing pulse) bp (broad pulse) tcs interlaced tcs interlaced tcs non-interlaced mla037 - 2 64 m s 64 m s lsp, ep and bp are combined to give tcs as shown. all timings are measured from falling edge of lsp. line numbers placed in the middle of the line. equivalent count numbers in brackets. fig.7 composite sync waveforms.
1996 nov 04 15 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 fig.8 odd/even timing. handbook, full pagewidth 621 622 623 624 (311) (310) (308) (309) 625 (312) 1 2 3 4 5 6 309 310 312 313 314 (1) 315 (2) 316 (3) 317 (4) 318 (5) 319 (6) 311 2 m s 2 m s odd / even output (normal sync mode when vcs to scs mode active) odd / even output (normal sync mode) tcs interlaced mla416 - 2 48 m s 30 m s 16 m s (1) 7 odd / even output (slave sync mode) 320 (7) second field start (odd) first field start (even) odd / even output (normal sync mode when vcs to scs mode active) odd / even output (normal sync mode) tcs interlaced odd / even output (slave sync mode) 30 m s (1) line numbers placed in the middle of the line. equivalent count numbers in brackets. (1) or 62 m s if register 1 d2.d1.d0 equals 1 1 1.
1996 nov 04 16 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 on-chip memory page memory organization the organization of the page memory is illustrated by fig.9. the ivt1.8* provides an additional row as compared with first generation decoders; this brings the display format up to 40 characters by 25 rows. rows 0 to 23 form the teletext page; row 24 is the extra row available for software generated status messages and flof/fastext prompt information. fig.9 basic page memory organization. handbook, full pagewidth mbd789 7 characters for status 8 characters always rolling (time) fixed character written by ivt hardware: alphanumerics white for normal; alphanumerics green when looking for display page 71 8 24 24 characters from page header rolling when display page looked for 5 to 20 0 1 2 3 4 row 21 22 23 24 25 main page display area packet x / 22 packet x / 23 packet x / 24 stored here if r0d7 = 1 10 14 10 bytes for received page information if enabled 14 bytes reserved in chapter 5 for vps data r emark to fig.9 row 0 row 0 is for the page header. the first seven characters (0 to 6) are free for status messages. character 8 is an alphanumeric white or green control character, written automatically by ivt1.8* to give a green rolling header when a page is being looked for. the last eight characters are for rolling time. row 25 the first 10 bytes of row 25 contain control data relating to the received page as shown in table 5. the remaining 14 bytes are free for use by the microcomputer.
1996 nov 04 17 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 table 5 row 25 received control data format row 25 d0 pu0 pt0 mu0 mt0 hu0 ht0 c7 c11 mag0 0 d1 pu1 pt1 mu1 mt1 hu1 ht1 c8 c12 mag1 0 d2 pu2 pt2 mu2 mt2 hu2 c5 c9 c13 mag2 0 d3 pu3 pt3 mu3 c4 hu3 c6 c10 c14 0 0 d4 ham.er ham.er ham.er ham.er ham.er ham.er ham.er ham.er found 0 d5 0 0 0 0 0 0 0 0 0 pblf d60000000000 d70000000000 column 0 1 2 3 4 5 6 7 8 9 table 6 page number and sub-code for table 5 bit name description page number mag magazine pu page units pt page tens pblf page being looked for found low for page has been found ham.er hamming error in corresponding byte page sub-code mu minutes units mt minutes tens hu hours units ht hours tens c4 to c14 transmitted control bits
1996 nov 04 18 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 extension packet memory organization when in normal extension packet enabled mode the rows of information are organized as illustrated in fig.10. row 23 of the extension page, as shown in fig.10, contains packet 8/30. packet 8/30 is mapped into the ivt1.8* memory as follows: 8 / 30 / 0 and 8 / 30 / 1 to chapter 4 row 23 8 / 30 / 2 and 8 / 30 / 3 to chapter 5 row 23 8 / 30 / 4 to 8 / 30 / 15 to chapter 6 row 23. fig.10 organization of the extension memory. (1) row 25 reserved for vps data in chapter 5. handbook, full pagewidth packets x/26/0 to x/26/14 packet x/28/2 packets x/27/0 to x/27/1 packets x/27/4 to x/27/5 packet x/24 if r0d7 = 0 packet x/25 packet x/28/0 packet 8/30 packet x/28/1 reserved row 0 to 14 15 16 17 18 19 20 21 22 23 24 25 mbd791 (1)
1996 nov 04 19 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 e nhanced mode in enhanced mode, the number of extension packets captured is reduced to the minimum required for fastext operation. the first seven chapters can then be used for storage, using the system of pointers. the arrangement of extension packets is shown in fig.11. when in enhanced mode and extension packets are disabled, normal 8-page mode is in operation, but the x/26 engine is enabled (unlike normal 8-page mode). fig.11 organization of the extension memory in enhanced mode. handbook, halfpage mbd788 packets 8 / 30 / 0,1 packets 8 / 30 / 2,3 packets 8 / 30 / 4 to 15 17 16 18 row not used 19 to 24 not used not used chapter 6 packets 27 / 0 chapter 6 packet 24 14 13 15 12 chapter 5 packets 27 / 0 chapter 5 packet 24 11 10 chapter 4 packets 27 / 0 chapter 4 packet 24 9 8 chapter 3 packets 27 / 0 chapter 3 packet 24 7 6 chapter 2 packets 27 / 0 chapter 2 packet 24 5 4 chapter 1 packets 27 / 0 chapter 1 packet 24 3 2 chapter 0 packets 27 / 0 chapter 0 packet 24 1 0
1996 nov 04 20 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 vpt data memory organization to simplify the software for dual-standard vpt decoders, the vps data from line 16 is stored in row 25 of chapter 5 of the page memory, and is aligned to match the packet 8/30 format 2 data as far as possible. the 8/30 format 2 packet is hamming coded and by setting the appropriate register control bit the data is stored after hardware hamming correction. there are 4 data bits stored in each column address of memory with an additional hamming error bit. the data equivalent to the vps signal is found in columns 12 to 19. although the vps data is not hamming protected, it is stored with 4 data bits per column address in the same way with an additional biphase error bit. the extra space in row 25 is allocated to two more line 16 words. they are word 15 (reserved) and word 4 (program source identification, ascii sequential) which may be useful for future applications. details of the memory organization are shown in fig.12. the stored data can be read from memory via the i 2 c-bus in the normal way. multiple reception/majority error correction of the vps data is the responsibility of the control software, the device simply stores the data as transmitted after biphase decoding. as both vps and 8/30/2 signals are stored in separate memory locations, it is possible to deal with future situations where both system a and system b transmissions may be present on the same tv channel, the defaults and level of service chosen by the control software. fig.12 detailed memory organization. handbook, full pagewidth mbd787 2 13 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 b11 b12 b13 b14 b15 b13 b14 b15 b16 b17 b18 b19 b20 b21 b22 b23 b24 b25 initial page d received page information column 8/30/2 vps 22 21 23 24 25 26 27 28 29 30 11 12 13 14 15 16 17 18 19 column 8/30/2 vps 0 20 status display b4 b5
1996 nov 04 21 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 register maps ivt1.8* mode registers r0 to r13 are shown in table 7. r0 to r10, r12 and r13 are write only; r11 is read/write, r11b is read only. register map (r3), for page requests, is shown in detail in table 11. table 7 register map (notes 1 to 4) register d7 d6 d5 d4 d3 d2 d1 d0 name no. advanced control 0 x/24 pos free run pll auto odd/even disable hdr roll cbb slave sync disable odd/even vcr mode r1 1/r11b select mode 1 vcs to scs 7 + p/ 8-bit acq on/off ext pkt enable dew/ full field tcs on t1 t0 page request address 2 ham check 27, 8/30 bank select a2 acq cct a1 acq cct a0 0 sc2 sc1 sc0 page request data 3 --- prd4 prd3 prd2 prd1 prd0 display chapter 4 --- - freeze header only a2 a1 a0 display control (normal) 5 bkgnd out bkgnd in cor out cor in text out text in pon out pon in display control (news?ash /subtitle) 6 bkgnd out bkgnd in cor out cor in text out text in pon out pon in display mode 7 status btm/top cursor on conceal/ reveal on t op/btm half single/ double height box on 24 box on 1 to 23 box on 0 active chapter 8 --- vps enable clear mem a2 a1 a0 cursor row 9 --- r4 r3 r2 r1 r0 cursor column 10 -- c5 c4 c3 c2 c1 c0 cursor data 11 d7 d6 d5 d4 d3 d2 d1 d0 device status 11b 625/525 sync rom ver r4 rom ver r3 rom ver r2 rom ver r1 rom ver r0 text signal quality vcs signal quality advanced control 2a 12 h3 h2 h1 h0 s3 s2 s1 s0 advanced control 2b 13 enhanc mode cursor freeze/ device ident meshing enable vps enable points enable ham check 24:18 disable pkt x/26 auto display pkt x/24
1996 nov 04 22 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 notes to table 7 1. the dash ( - ) indicates these bits are inactive and must be written to logic 0 for future compatibility. 2. certain registers are auto-incremented following an i 2 c-bus transmission byte. these are register r0 to r3, r4 to r7 and r8 to r12 or r13. 3. all bits in registers r0 to r13 are cleared to logic 0 on power-up except bits d0 and d1 of registers r1, r5 and r6 which are set to logic 1. 4. all memory is cleared to space (00100000) on power-up, except row 0 column 7 chapter 0, which is alpha white (00000111) as the acquisition circuit is enabled but all pages are on hold. table 8 register description register bit d0 to d7 function r0 avanced control - auto-increments to register 1 r1 1/r11b select selects reading of r11 if low or r11b if high. vcr mode if logic 1 selects short time constant mode of pll. disable odd/even forces odd/even output low when logic 1 (see table 9). cbb slave sync when set will modify internal slave sync timing to allow connection to sandcastle of philips one-chip tv ic (tda8362). disable hdr roll stops the display update of rolling time and green rolling header during page requests when logic 1. time updates on page reception only. auto odd/even if logic 1 then odd/even output only active when no tv picture displayed (see table 9). free run pll will force the display pll to free run at 6 mhz when logic 1. x/24 pos automatic display of fastext prompt row when logic 1. will also cause row 24 data transmitted by packet 26 to be written to display, rather than extension memory. r1 mode - auto-increments to register 2 t0, t1 interlace/non-interlace 312/313 line control (see table 10). tcs on text composite sync or direct sync select (see table 10 for ffb mode selection). dew/full field field-flyback or full-channel mode. ext pkt enable enables reception and storage of extension packets when logic 1. acq on/off acquisition circuits turned off when logic 1. 7 + p/8-bit 7 bits with parity checking or 8-bit mode. vcs to scs connects vcs from video sync separator to display ?eld sync detector to enable stable display of 60 hz status messages when logic 1. r2 page request address - auto-increments to register 3 sc0 to sc2 start column for page request data (see table 11). 0 must be logic 0 for normal operation. acq cct a0, a1 selects one of four acquisition circuits. bank select a2 selects bank of four pages being addressed for acquisition. ham check 27, 8/30 8/4 hamming check packet 27 and 8/30 data. r3 page request data - does not auto-increment prd0 to prd4 see table 11.
1996 nov 04 23 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 r4 display chapter - auto-increments to register 5 a0 to a2 selects one of 8 display chapters. freeze header only freezes the rolling header, but (unlike r0d4) allows the time to roll. r5 normal display control - auto-increments to register 6 r6 newsflash/subtitle display control - auto-increments to register 7; note 1 pon picture on. text text on. cor contrast reduction on. bkgnd background colour on. r7 display mode - does not auto-increment box on 0 boxing function allowed on row 0. box on 1 to 23 boxing function allowed on rows1 to 23. box on 24 boxing function allowed on row 24. single/double height to display double height text. t op/btm half to select bottom half of page when double height is logic 1. conceal/reveal on to reveal concealed text. cursor on to display cursor. status btm/top row 25 displayed above or below the main text. r8 active chapter - auto-increments to register 9 a0 to a2 active chapter for data written to or read from memory via the i 2 c-bus. clear mem when set to logic 1, clears the display memory. this bit is automatically reset. vps enable vps acquisition enabled when logic 1. r9 cursor row - auto-increments to register 10 r0 to r4 active row for data written to or read from memory via the i 2 c-bus. r10 cursor column - auto-increments to register 11 or 11b c0 to c5 active column for data written to or read from memory via the i 2 c-bus. r11 cursor data - does not auto-increment d0 to d7 data read from/written to memory via i 2 c-bus, at location pointed to by r9 and r10. this location automatically increments each time r11 is accessed. r11b device status - does not auto-increment vcs signal quality indicates that the video signal quality is good and pll is phase-locked to input video when logic 1. text signal quality if a good teletext signal is being received then logic 1. rom ver r0 to r4 indicated language/rom variant. for western european is logic 0. r3 and r4 are set high if r13 d6 is logic 1. 625/525 sync if the input video is a 525 line signal then logic 1. r12 advanced control 2a - does not auto-increment s0 to s3, h0 to h3 each acquisition channel can be programmed to process its page in one of four ways as shown in table 12. register bit d0 to d7 function
1996 nov 04 24 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 note 1. these functions have in and out referring to inside and outside the boxing function respectively. table 9 odd/even selection table 10 interlace/non-interlace 312/313 line control and odd/even ?eld detection option notes 1. x = don't care. 2. reverts to interlaced mode if a newsflash or subtitle is being displayed. r13 advanced control 2b - does not auto-increment auto display pkt x/24 status row will show the contents of the row of the extension memory (packet 24) when logic 1. disable pkt x/26 output taken from processing engine written to the display memory when logic 0. operates independent of the acquisition. ham check 24 : 18 when logic 1 all packet 26 data is stored in extension memory unchecked. points enable enable for acquisition pointers when logic 1. vps enable vps acquisition enabled when logic 1. meshing enable enables meshing display function in box mode. cursor freeze/ device ident when logic 1, cursor position not updated even if active row and column change. this bit will also cause r3 and r4 of the rom code in register r11b to be set high. this allows software to identify the device as an ivt1.8*. an internal 1.8 mode ?ag is also set, which enables the operation of r0d4, r4d4 and the subtitle bit in r3. enhanc mode when logic 1, extension packet data is mapped into the last chapter. only packet 24, 27/0 and 8/30 are stored. chapters 0 to 6 can then be used for page storage. if extension packets are not enabled, 8 pages are stored as normal, but x/26 engine is enabled. auto odd/even disable odd/even result 00 odd/even output continuous 01 odd/even statically low 11 odd/even active only when no tv picture displayed 11 dv output to indicate reception of error-free 8/30/format 2 packet or vps line tcs on ffb mode (1) t1 t0 result x 0 0 interlaced 312.5/312.5 lines x 0 1 non-interlaced 312/313 lines (note 2) x 1 0 non-interlaced 312/313 lines (note 2) 0 1 1 scs (scan composite sync) mode: ffb leading edge in ?rst broad pulse of ?eld 1 1 1 scs (scan composite sync) mode: ffb leading edge in second broad pulse of ?eld register bit d0 to d7 function
1996 nov 04 25 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 table 11 register map for page requests (r3); notes 1 to 6 notes 1. abbreviations are as given in table 6 except for do care bits and ch = chapter address for acquisition chapter. 2. when the do care bit is set to logic 1 this means the corresponding digit is to be taken into account for page requests. if the do care bit is set to logic 0 the digit is ignored. this allows, for example, normal or timed page selection. 3. if hold is set low, the page is held and not updated. 4. columns auto-increment on successive i 2 c-bus transmission bytes. 5. the subtitle bit is only present when the device is in 1.8 mode (i.e. r13d6 has been set high). 6. x = dont care. table 12 acquisition channel programming note 1. these register bits operate in conjunction with 7 + p/ 8-bit (register 1, bit d6) which will over-ride the choice of data checker if set, setting all channels to 8-bit only. if this bit is not set h0 to h3 and s0 to s3 will determine the data checking (default to 7-bit + parity). start column prd4 prd3 prd2 prd1 prd0 0 do care magazine hold mag2 mag1 mag0 1 do care page tens pt3 pt2 pt1 pt0 2 do care page units pu3 pu2 pu1 pu0 3 do care hours tens subtitle x ht1 ht0 4 do care hours units hu3 hu2 hu1 hu0 5 do care minutes tens x mt2 mt1 mt0 6 do care minutes units mu3 mu2 mu1 mu0 7 x x ch2 ch1 ch0 h0 to h3 (1) s0 to s3 (1) checking algorithm for acquisition channel x 0 0 7-bit + parity for whole page 0 1 8-bit for whole page 1 0 8/4 hamming check for whole page 11 mixed 8/4 hamming (columns 0 to 7, 20 to 27) and 7-bit + parity (columns 8 to 19, 28 to 39)
1996 nov 04 26 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 clock systems crystal oscillator the crystal is a conventional colpitts 3-pin design operating at 27 mhz. the oscillator is sinusoidal and linear, with a controlled output amplitude. this reduces the radiated and conducted level of the 27 mhz fundamental frequency, and reduces the power dissipation in the quartz crystal. it is capable of oscillating with both fundamental and third overtone mode crystals. external components should be used to suppress the fundamental output of the third overtone as illustrated in fig.13. the crystal characteristics are given in table 13. table 13 crystal characteristics (see fig.13) symbol parameter typ. max. unit crystal (27 mhz, 3rd overtone) c1 series capacitance 1.7 - pf c0 parallel capacitance 5.2 - pf c l load capacitance 20 - pf r r resonance resistance - 50 w r1 series resistance 20 -w x a ageing - 5 10 - 6 year - 1 x j adjustment tolerance - 25 10 - 6 x d drift - 25 10 - 6 fig.13 crystal oscillator application diagram for sot240-1; pins in parenthesis are for sot247-1. handbook, full pagewidth 3 2 saa5281 mbd786 4 1 8.2 pf crystal oscillator 100 nf 15 pf 1 nf 3.3 m h 3.3 k w (52) (1) (2) (3) oscgnd oscin oscout v dd1 27 mhz 3rd overtone
1996 nov 04 27 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 character sets the wst specification allows the selection of national character sets via the page header transmission bits, c12 to c14. the basic 96 character sets differ only in 13 national option characters as indicated in the tables 21, 22 and 23 with reference to their table position in the basic character matrix illustrated in table 20. the ivt1.8* automatically decodes transmission bits c12 to c14. tables 14, 15 and 16 illustrate the character matrixes. character bytes are listed as transmitted from b1 to b7. meshing this is an alternative method of displaying teletext subtitles, or similar boxed text superimposed on the tv picture and operates by showing reduced contrast tv pictures in place of the (black) background within the boxed area. the meshing effect is produced by toggling the blan signal from ivt at pixel rate. by starting at the same point each field, and toggling the start position each line, a chequered pattern will result. this allows movement to be seen behind the text information. the mesh off/on bit in register 13 d5 controls this function. normally at zero, compatibility with ivt1.0 is maintained. fig.14 character format. handbook, full pagewidth mla663 alphanumerics and graphics 'space' character 0000010 alphanumerics character 1011010 alphanumerics or blast-through alphanumerics character 0001001 alphanumerics character 1111111 contiguous graphics character 1111111 separated graphics character 1111111 separated graphics character 0110111 contiguous graphics character 0110111 background colour display colour = =
1996 nov 04 28 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 table 14 saa5281p/e character data input decoding, west european languages; notes 1 to 9 for character version number (11000) see register 11b . handbook, full pagewidth mba429 normal height b 4 b 3 b 2 b 1 b 5 b 6 b 7 b 8 0 1 22a3 3a4 5 6 6a 77a 8 912131415 column r o w b i t s 0 0 0 0 0 0 0 1 0 or 1 0 1 0 0 0 1 1 0 or 1 0 1 1 0 0 1 1 0 1 0 0 0 1 0 1 1 0 0 0 1 0 0 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 0 0 1 1 1 14 1 1 1 0 so hold graphics 15 1 1 1 1 si release graphics 11 1 0 1 1 start box esc 12 1 1 0 0 black back - ground 13 1 1 0 1 double height new back - ground 10 1 0 1 0 end box separated graphics 9 1 0 0 1 steady contiguous graphics 8 1 0 0 0 flash conceal display 7 0 1 1 1 alpha - numerics white graphics white 6 0 1 1 0 alpha - numerics cyan graphics cyan 5 0 1 0 1 alpha - numerics magenta graphics magenta 4 0 1 0 0 alpha - numerics blue graphics blue 3 0 0 1 1 alpha - numerics yellow graphics yellow 2 0 0 1 0 alpha - numerics green graphics green 0 0 0 0 0 alpha - numerics black graphics black 1 0 0 0 1 alpha - numerics red graphics red (2) (2) (2) (2) (1) (2) (2) (1) (2) (1)
1996 nov 04 29 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 table 15 saa5281p/h character data input decoding, east european languages; notes 1 to 9 for character version number (11001) see register 11b. handbook, full pagewidth mla961 normal height b 4 b 3 b 2 b 1 b 5 b 6 b 7 b 8 0 1 22a3 3a4 5 6 6a 77a 8 912131415 column r o w b i t s 0 0 0 0 0 0 0 1 0 or 1 0 1 0 0 0 1 0 0 or 1 0 1 1 0 0 1 1 0 1 0 0 0 1 0 1 1 0 0 0 1 0 0 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 0 0 1 1 1 14 1 1 1 0 so hold graphics 15 1 1 1 1 si release graphics 11 1 0 1 1 start box esc 12 1 1 0 0 black back - ground 13 1 1 0 1 double height new back - ground 10 1 0 1 0 end box separated graphics 9 1 0 0 1 steady contiguous graphics 8 1 0 0 0 flash conceal display 7 0 1 1 1 alpha - numerics white graphics white 6 0 1 1 0 alpha - numerics cyan graphics cyan 5 0 1 0 1 alpha - numerics magenta graphics magenta 4 0 1 0 0 alpha - numerics blue graphics blue 3 0 0 1 1 alpha - numerics yellow graphics yellow 2 0 0 1 0 alpha - numerics green graphics green 0 0 0 0 0 alpha - numerics black graphics black 1 0 0 0 1 alpha - numerics red graphics red (2) (2) (2) (2) (1) (2) (2) (1) (2) (1)
1996 nov 04 30 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 table 16 saa5281p/t character data input decoding, west european and turkish languages; notes 1 to 9 for character version number (11010) see register 11b. handbook, full pagewidth mba431 normal height b 4 b 3 b 2 b 1 b 5 b 6 b 7 b 8 0 1 22a3 3a4 5 6 6a 77a 8 912131415 column r o w b i t s 0 0 0 0 0 0 0 1 0 or 1 0 1 0 0 0 1 1 0 or 1 0 1 1 0 0 1 1 0 1 0 0 0 1 0 1 1 0 0 0 1 0 0 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 0 0 1 1 1 14 1 1 1 0 so hold graphics 15 1 1 1 1 si release graphics 11 1 0 1 1 start box esc 12 1 1 0 0 black back - ground 13 1 1 0 1 double height new back - ground 10 1 0 1 0 end box separated graphics 9 1 0 0 1 steady contiguous graphics 8 1 0 0 0 flash conceal display 7 0 1 1 1 alpha - numerics white graphics white 6 0 1 1 0 alpha - numerics cyan graphics cyan 5 0 1 0 1 alpha - numerics magenta graphics magenta 4 0 1 0 0 alpha - numerics blue graphics blue 3 0 0 1 1 alpha - numerics yellow graphics yellow 2 0 0 1 0 alpha - numerics green graphics green 0 0 0 0 0 alpha - numerics black graphics black 1 0 0 0 1 alpha - numerics red graphics red (2) (2) (2) (2) (1) (2) (2) (1) (2) (1)
1996 nov 04 31 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 table 17 saa5281p/r character data input decoding, baltic and cyrillic languages; notes 1 to 9 for character version number (00101) see register 11b. handbook, full pagewidth normal height b 4 b 3 b 2 b 1 b 5 b 6 b 7 b 8 0 1 22a3 3a4 5 6 6a 77a 8 912131415 column r o w b i t s 0 0 0 0 0 0 0 1 0 or 1 0 1 0 0 0 1 1 0 or 1 0 1 1 0 0 1 1 0 1 0 0 0 1 0 1 1 0 0 0 1 0 0 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 0 0 1 1 1 14 1 1 1 0 so hold graphics 15 1 1 1 1 si release graphics 11 1 0 1 1 start box twist 12 1 1 0 0 black back - ground 13 1 1 0 1 double height new back - ground 10 1 0 1 0 end box separated graphics 9 1 0 0 1 steady contiguous graphics 8 1 0 0 0 flash conceal display 7 0 1 1 1 alpha - numerics white graphics white 6 0 1 1 0 alpha - numerics cyan graphics cyan 5 0 1 0 1 alpha - numerics magenta graphics magenta 4 0 1 0 0 alpha - numerics blue graphics blue 3 0 0 1 1 alpha - numerics yellow graphics yellow 2 0 0 1 0 alpha - numerics green graphics green 0 0 0 0 0 alpha - numerics black graphics black 1 0 0 0 1 alpha - numerics red graphics red mba648 - 1 (1) (1) (2) (2) (2) (2) (2) (2) (2)
1996 nov 04 32 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 table 18 saa5281p/l character data input decoding, arabic and hebrew languages; notes 1 to 9 for character version number (00100) see register 11b . handbook, full pagewidth mla963 - 1 normal height b 4 b 3 b 2 b 1 b 5 b 6 b 7 b 8 0 1 22a3 3a4 5 6 6a 77a 8 912131415 column r o w b i t s 0 0 0 0 0 0 0 1 0 or 1 0 1 0 0 0 1 0 0 or 1 0 1 1 0 0 1 1 0 1 0 0 0 1 0 1 1 0 0 0 1 0 0 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 14 1 1 1 0 so hold graphics 15 1 1 1 1 si release graphics 11 1 0 1 1 start box twist 12 1 1 0 0 black back - ground 13 1 1 0 1 double height new back - ground 10 1 0 1 0 end box separated graphics 9 1 0 0 1 steady contiguous graphics 8 1 0 0 0 flash conceal display 7 0 1 1 1 alpha - numerics white graphics white 6 0 1 1 0 alpha - numerics cyan graphics cyan 5 0 1 0 1 alpha - numerics magenta graphics magenta 4 0 1 0 0 alpha - numerics blue graphics blue 3 0 0 1 1 alpha - numerics yellow graphics yellow 2 0 0 1 0 alpha - numerics green graphics green 0 0 0 0 0 alpha - numerics black graphics black 1 0 0 0 1 alpha - numerics red graphics red 0 1 1 0 0 or 1 1 1 0 0 1 1 1 0 or 1 1 1 1 (1) (1) (2) (2) (2) (2) (2) (2) (2)
1996 nov 04 33 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 table 19 saa5281p/k character data input decoding, french and arabic languages; notes 1 to 9 for character version number (00100) see register 11b . handbook, full pagewidth mla972 - 1 normal height b 4 b 3 b 2 b 1 b 5 b 6 b 7 b 8 0 1 22a3 3a4 5 6 6a 77a 8 912131415 column r o w b i t s 0 0 0 0 0 0 0 1 0 or 1 0 1 0 0 0 1 0 0 or 1 0 1 1 0 0 1 1 0 1 0 0 0 1 0 1 1 0 0 0 1 0 0 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 14 1 1 1 0 so hold graphics 15 1 1 1 1 si release graphics 11 1 0 1 1 start box twist 12 1 1 0 0 black back - ground 13 1 1 0 1 double height new back - ground 10 1 0 1 0 end box separated graphics 9 1 0 0 1 steady contiguous graphics 8 1 0 0 0 flash conceal display 7 0 1 1 1 alpha - numerics white graphics white 6 0 1 1 0 alpha - numerics cyan graphics cyan 5 0 1 0 1 alpha - numerics magenta graphics magenta 4 0 1 0 0 alpha - numerics blue graphics blue 3 0 0 1 1 alpha - numerics yellow graphics yellow 2 0 0 1 0 alpha - numerics green graphics green 0 0 0 0 0 alpha - numerics black graphics black 1 0 0 0 1 alpha - numerics red graphics red 0 1 1 0 0 or 1 1 1 0 0 1 1 1 0 or 1 1 1 1 (1) (1) (2) (2) (2) (2) (2) (2) (2)
1996 nov 04 34 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 notes to tables 14, 15, 16, 17, 18 and 19 1. these control characters are reserved for compatibility with other data codes. 2. these control characters are presumed before each row begins. 3. control characters shown in columns 0 and 1 are normally displayed as spaces. 4. characters may be referred to by column and row (for example 2/5 refers to %). 5. black represents displayed colour. white represents background. 6. the saa5281 national option characters are illustrated in tables 21, 22 and 23. 7. characters 8/6, 8/7, 9/5, 9/6 and 9/7 are special characters for combining with character 8/5 (e, h and t codes only). characters 5/12, 5/13, 5/14 and 5/15 are combined with 5/11 (s code only). 8. national option characters will be displayed according to the setting of control bits c12 to c14. these will be mapped into the basic code table into positions shown in tables 21, 22 and 23. 9. columns 2a, 3a, 6a and 7a are displayed in graphics mode.
1996 nov 04 35 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 table 20 saa5281 basic character matrix; note 1 note 1. where nc = national option character position. f ull pagewidth mla630 2/1 2/0 2/8 3/0 3/8 4/0 4/8 5/0 5/8 7/8 6/8 7/0 nc 6/0 nc 2/9 3/1 3/9 4/1 4/9 5/1 5/9 6/1 6/9 7/1 7/9 2/2 2/10 3/2 3/10 4/2 4/10 5/2 5/10 6/2 6/10 7/2 7/10 2/11 3/3 3/11 4/3 4/11 5/3 6/3 6/11 7/3 2/12 3/4 3/12 4/4 4/12 5/4 6/4 6/12 7/4 2/5 2/13 3/5 3/13 4/5 4/13 5/5 6/5 6/13 7/5 2/6 2/14 3/6 3/14 4/6 4/14 5/6 6/6 7/6 2/7 2/15 3/7 3/15 4/7 4/15 5/7 6/7 6/15 7/7 7/15 2/3 nc 5/11 nc 5/12 nc 5/13 nc 5/14 nc 5/15 nc 7/11 nc 7/12 nc 7/13 nc 7/14 nc 2/4 nc
1996 nov 04 36 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 table 21 saa5281p/e national option character set table 22 saa5281p/h national option character set h andbook, full pagewidth mlb458 language c12 c13 c14 phcb 000 001 010 011 100 french italian swedish german english 2 / 3 2 / 4 4 / 0 5 / 11 5 / 12 5 / 13 5 / 14 5 / 15 6 / 0 7 / 11 7 / 12 7 / 13 7 / 14 character position (column / row) spanish 101 (1) (1) phcb are the page header control bits. other combinations default to english. handbook, full pagewidth mla966 language c12 c13 c14 phcb (1) 000 001 010 101 110 111 rumanian czechoslovakia serbo-croat swedish german polish 2 / 3 2 / 4 4 / 0 5 / 11 5 / 12 5 / 13 5 / 14 5 / 15 6 / 0 7 / 11 7 / 12 7 / 13 7 / 14 character position (column / row) (1) phcb are the page header control bits. other combinations default to german. only the above characters change with the phcb. all other characters in the basic set are shown in table 20.
1996 nov 04 37 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 table 23 saa5281p/t national option character set a ndbook, full pagewidth mba430 language c12 c13 c14 phcb (1) 000 001 110 011 100 101 spanish french italian turkish german english 2 / 3 2 / 4 4 / 0 5 / 11 5 / 12 5 / 13 5 / 14 5 / 15 6 / 0 7 / 11 7 / 12 7 / 13 7 / 14 character position (column / row) (1) phcb are the page header control bits. other combinations default to english. only the above characters change with the phcb. all other characters in the basic set are shown in table 20.
1996 nov 04 38 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 table 24 saa5281p/r national option character set (1) phcb are the page header control bits. other combinations default to estonian. ha ndbook, full pagewidth language c12 c13 c14 phcb (1) 010 011 100 russian lettish / lithuanian estonian 2 / 3 2 / 4 4 / 0 5 / 11 5 / 12 5 / 13 5 / 14 5 / 15 6 / 0 7 / 11 7 / 12 7 / 13 7 / 14 character position (column / row) mea597 234567 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1996 nov 04 39 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 table 25 saa5281p/k national option character set (1) phcb are the page header control bits. other combinations default to french. ha ndbook, full pagewidth mla968 - 1 language (c12, c13, c14) phcb (1) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 234567 234567 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 arabic french 1 0 0 1 1 1
1996 nov 04 40 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 table 26 saa5281p/l national option character set (1) phcb are the page header control bits. other combinations default to hebrew english. ha ndbook, full pagewidth mla967 language (c12, c13, c14) phcb (1) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 234567 234567 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 arabic hebrew/english 1 0 1 1 1 1
1996 nov 04 41 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 application information fig.15 application diagram for sdip52, sot247-1. handbook, full pagewidth mbd790 1 100 nf 10 k w 15 pf 8.2 pf 22 nf 3.3 3.3 m h 27 mhz 3rd overtone 2 3 4 5 6 7 100 nf 8 100 nf 9 100 nf 10 27 k w 11 33 m f 100 nf 12 5 v cvbs 13 14 1.5 k w 330 nf 15 1 k w 16 17 18 19 20 21 22 sync r g b 23 24 25 26 blan cor odd/even cor odd/even saa5281 27 28 29 30 31 32 33 34 35 36 37 39 38 40 41 42 43 44 45 46 47 48 49 50 52 51 5 v 5 v 83c654 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 27 28 29 30 31 32 33 34 35 36 37 39 38 40 26 25 24 23 22 21 1 sda scl 220 w 220 w link options 4.7 k w 4.7 k w 5 v line 23 470 w 5 v pdi pl out pon 5 v 5 v pcf8572 pcf8582 18 27 36 45 5 v 3.3 nf 56 k w 5 v address select i.c. i.c. i.c. i.c. i.c. i.c. i.c. i.c. clk o/p line 23 clk en i.c. i.c. n.c. n.c. i.c. i.c. i.c. i.c. i.c. i.c. v ss3 oscout oscin oscgnd ref+ n.c. black cvbs iref v dd2 pol v ss1 v ss1 sttv/lfb vcr/ffb v ss2 r g b rgbref blan y scl sda i.c. i.c. i.c. v dd1 i.c. m f m f v ss xtal1 xtal2 p3.0 p3.1 p3.2 p3.3 p3.4 p3.5 p3.6 p3.7 p1.5 scl sda rst p1.1 p1.2 p1.3 p1.4 p1.0 p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 dd p0.0 p0.1 p0.2 p0.3 v p0.4 p0.5 p0.6 p0.7 ea ale psen
1996 nov 04 42 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 package outlines unit a max. 1 2 b 1 cd e e m h l references outline version european projection issue date iec jedec eiaj mm inches dimensions (inch dimensions are derived from the original mm dimensions) sot240-1 92-11-17 95-01-25 a min. a max. b z max. w m e e 1 1.4 1.14 0.53 0.38 0.36 0.23 62.60 61.60 14.22 13.56 3.90 3.05 0.254 2.54 15.24 15.88 15.24 18.46 15.24 2.1 4.9 0.36 4.06 0.055 0.045 0.021 0.015 0.014 0.009 2.46 2.42 0.56 0.53 0.15 0.12 0.01 0.10 0.60 0.63 0.60 0.73 0.60 0.083 0.19 0.014 0.16 m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 48 1 25 24 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. (1) (1) (1) dip48: plastic dual in-line package; 48 leads (600 mil) sot240-1
1996 nov 04 43 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 unit b 1 cee m h l references outline version european projection issue date iec jedec eiaj mm dimensions (mm are the original dimensions) sot247-1 90-01-22 95-03-11 b max. w m e e 1 1.3 0.8 0.53 0.40 0.32 0.23 47.9 47.1 14.0 13.7 3.2 2.8 0.18 1.778 15.24 15.80 15.24 17.15 15.90 1.73 5.08 0.51 4.0 m h c (e ) 1 m e a l seating plane a 1 w m b 1 d a 2 z 52 1 27 26 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. (1) (1) d (1) z e a max. 12 a min. a max. sdip52: plastic shrink dual in-line package; 52 leads (600 mil) sot247-1
1996 nov 04 44 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 unit a 1 a 2 a 3 b p ce (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 0.25 0.05 2.90 2.65 0.25 0.50 0.35 0.25 0.14 14.1 13.9 1 18.2 17.6 1.4 1.2 1.2 0.8 7 0 o o 0.2 0.1 0.2 1.95 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 1.0 0.6 sot319-2 92-11-17 95-02-04 d (1) (1) (1) 20.1 19.9 h d 24.2 23.6 e z 1.2 0.8 d e q e a 1 a l p q detail x l (a ) 3 b 19 y c e h a 2 d z d a z e e v m a 1 64 52 51 33 32 20 x pin 1 index b p d h b p v m b w m w m 0 5 10 mm scale qfp64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm sot319-2 a max. 3.20
1996 nov 04 45 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). soldering by dipping or by wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joint for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg max ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. repairing soldered joints apply a low voltage soldering iron (less than 24 v) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
1996 nov 04 46 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 notes
1996 nov 04 47 philips semiconductors preliminary speci?cation integrated video input processor and teletext decoder (ivt1.8*) saa5281 notes
internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1996 sca52 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 247 9145, fax. +7 095 247 9144 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: rua do rocio 220, 5th floor, suite 51, 04552-903 s?o paulo, s?o paulo - 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